To calculate the $N$-divide factors for a Phase-Locked Loop (PLL) Frequency-Shift Keying (FSK) modulator, we use the formula:

$f_{\text{output}} = N \times f_{\text{reference}}$

where:

• $f_{\text{output}}$ is the desired output frequency,
• $f_{\text{reference}}$ is the reference input frequency,
• $N$ is the divide factor.

Given:

• $f_{\text{reference}} = 1 \, \text{MHz}$,
• For binary 0, $f_{\text{output}} = 1.3 \, \text{GHz}$,
• For binary 1, $f_{\text{output}} = 1.45 \, \text{GHz}$.

Step 1: Calculate $N_0$ for binary 0

For binary 0, we have: $1.3 \, \text{GHz} = N_0 \times 1 \, \text{MHz}$ $N_0 = \frac{1.3 \, \text{GHz}}{1 \, \text{MHz}} = \frac{1.3 \times 10^9}{1 \times 10^6} = 1300$

Step 2: Calculate $N_1$ for binary 1

For binary 1, we have: $1.45 \, \text{GHz} = N_1 \times 1 \, \text{MHz}$ $N_1 = \frac{1.45 \, \text{GHz}}{1 \, \text{MHz}} = \frac{1.45 \times 10^9}{1 \times 10^6} = 1450$

Conclusion

• The divide factor $N_0$ for binary 0 is 1300.
• The divide factor $N_1$ for binary 1 is 1450.

Would you like more details or have any other questions?

Here are five questions to expand on this topic:

1. How does the reference frequency affect the performance of a PLL modulator?
2. What is the role of the divide factor $N$ in a PLL?
3. How would you design the loop filter for this PLL modulator?
4. Can the same PLL be used for different modulation schemes like QAM?
5. What happens if the reference input is not stable?

Tip: The accuracy of a PLL modulator greatly depends on the stability and precision of the reference frequency source.