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Let us break down and solve **Exercises 3, 4, and 5** from the assignment:

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### **Exercise 03**
#### Part (a): Design a combinatorial circuit that detects the parity of a 4-bit sequence \( A, B, C, D \)
- **Parity Definition**: Parity is even when the number of 1's is even, and odd when the number of 1's is odd.
- **Output \( P \)**: \( P = 0 \) for even parity, \( P = 1 \) for odd parity.

**Solution**:
To compute parity:
1. Use XOR gates since XOR outputs a high signal (1) when there is an odd number of 1's.
2. Boolean equation: \( P = A \oplus B \oplus C \oplus D \), where \( \oplus \) represents XOR.

**Circuit Diagram**:
- Connect inputs \( A, B, C, D \) to a chain of XOR gates:
  - First XOR: \( T_1 = A \oplus B \)
  - Second XOR: \( T_2 = T_1 \oplus C \)
  - Final XOR: \( P = T_2 \oplus D \)

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#### Part (b): Implement using a \( 16 \times 1 \) MUX
To implement parity detection using a \( 16 \times 1 \) multiplexer:
1. Treat \( A, B, C, D \) as the 4 selection lines of the MUX.
2. The MUX will have \( 16 \) inputs corresponding to all possible combinations of \( A, B, C, D \).
3. For each combination:
   - Set the MUX input to 1 if the combination has an odd number of 1's (parity = 1).
   - Otherwise, set the MUX input to 0.

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### **Exercise 04**
#### Part (a): Design a logic circuit for the 2's complement of a 3-bit binary number
- **Steps to Compute 2's Complement**:
  1. Invert all bits of the number (1's complement).
  2. Add \( 1 \) to the least significant bit (LSB).

**Circuit Description**:
1. Use NOT gates to invert all 3 bits (\( A, B, C \)).
2. Use a **Half Adder** or **Full Adder** to add \( 1 \) to the inverted bits.

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#### Part (b): Use Half Adders
- Use one Half Adder for the least significant bit addition:
  - \( C' + 1 \)
  - Carry from the LSB propagates to a Full Adder for \( B' + \text{Carry} \).
- Repeat for the remaining bits.

#### Part (c): Use \( 8 \times 1 \) Multiplexer
- Inputs: Original 3-bit number (\( A, B, C \)).
- Control: Use MUX inputs to define outputs based on 2's complement truth table.

#### Part (d): Use \( 1 \times 8 \) Demultiplexer
- Invert the bits using NOT gates before connecting to Demux inputs.

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### **Exercise 05**
#### Boolean Function: \( X = AB' + B'C + A'BC' \)
#### Part (a): Using a \( 3 \times 8 \) Decoder
1. Use \( A, B, C \) as inputs to the \( 3 \times 8 \) decoder.
2. Enable decoder outputs corresponding to minterms of the function:
   - \( AB' \): Enable output \( 2 \) (\( 010 \)).
   - \( B'C \): Enable output \( 4 \) (\( 100 \)).
   - \( A'BC' \): Enable output \( 1 \) (\( 001 \)).

3. Combine outputs using OR gates.

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#### Part (b): Using an \( 8 \)-input Multiplexer
1. Use \( A, B, C \) as MUX select lines.
2. Set MUX inputs \( I_0, I_1, ..., I_7 \) to match truth table values of \( X \).

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#### Part (c): Using XOR Gate and \( 2:1 \) MUX
1. Rearrange the function: \( X = (A \oplus B) \cdot C + A'BC' \).
2. Implement \( A \oplus B \) with XOR, then combine with \( C \) and \( A'BC' \).

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#### Part (d): Using \( 4:1 \) MUX
1. Use \( B, C \) as MUX control inputs.
2. Simplify terms and connect \( A \) and constants to the MUX inputs.

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Would you like to see the detailed steps or diagrams for any specific part? Here are some follow-up questions to consider:

1. Do you need truth tables for any exercise?
2. Should I detail the XOR implementation for parity detection?
3. Would you like examples of simplifying Boolean expressions?
4. Do you need a full diagram of the \( 16 \times 1 \) MUX implementation?
5. Do you need help with Half Adder logic for the 2's complement?

**Tip**: For Boolean simplifications, always check for common terms to minimize gates!

Explore solutions for designing logic circuits for parity detection, computing the 2's complement of a 3-bit number, and implementing Boolean functions using multiplexers and decoders. Learn detailed steps, Boolean algebra principles, and circuit design techniques. Suitable for first-year undergraduate students.

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